The present invention relates to a fast calculation circuit for a cyclic redundancy check code used in detecting data error, and more particularly to a fast calculation circuit capable of calculating at high speeds a cyclic redundancy check code particularly for compressed coded data.
In recent data storage apparatuses using a magnetic tape, there has been adopted a method of compressing data by a compression circuit and storing the compressed data in a magnetic tape in order to increase the capacity of data storage. After the compression circuit compresses raw data sent from a CPU or the like by using a run length method for example, a cyclic redundancy check code (hereinafter called CRCC) is calculated in accordance with a generating polynomial, and the calculated CRCC is compared with a CRCC of the raw data to detect data error.
With data compression through such a run length method, if there are consecutive same data bytes in raw data, the consecutive data bytes are transformed into compressed data constructed of the data content and the number of consecutive data bytes. Therefore, data after subjected to such transformation include therein the compressed data and the data not compressed because of its discontinuity. The length of data to be compressed is, for example, a maximum of 255 bytes, and the data applicable to compression are, for example, a maximum of 256 types.
With a conventional calculation circuit for a CRCC, data after subjected to transformation include therein compressed and uncompressed data and a CRCC is calculated after the raw data are restored from the compressed data. Therefore, there arises a problem that a long operation time is required.
A technique of calculating a CRCC is known, for example, in JP-A-57-25046.